8-Bit Software

The BBC and Master Computer Public Domain Library

Inside The BBC B+

Back to 8BS
[Back to Insides]
BBC B+ Motherboard

BBC model B+


74LS123 (TTL Dual retriggerable monostable multivibrator, MMV) (8271 Disc Interface only)
See IC15


74LS393 (TTL Dual 4-bit binary counter) (8271 Disc Interface only)
See IC15


4013 (CMOS Dual D-flipflop) (8271 Disc Interface only)
See IC15


4521B (CMOS 24-stage binary counter/divider) (8271 Disc Interface only)
See IC15


74LS244 (TTL Octal buffer)
Buffers the data lines for the printer port.


74LS244 (TTL Octal buffer)
Buffers the control lines for the 1MHz expansion bus.


7438 (TTL Quad 2-input NAND gate, open collector)
Buffers several lines of the floppy disc interface.
See IC15,IC16


7416 (TTL Hex inverter, open collector)
Buffers several lines of the floppy disc interface.
See IC15,IC16


74LS00 (TTL Quad 2-input NAND gate) (8271 Disc Interface only)
See IC15


6522 (Versatile Interface Adapter, VIA)
A VIA has two sets of 8 I/O lines with two associated control lines, known as Ports A and B. Each I/O line can be set to input or output individually using the VIA's Data Direction registers; the control lines (CA1/CA2, CB1/CB2) act as handshake signals for their respective ports. The input and output registers are latched. The VIA also contains two 16-bit programmable timer/counters and a shift register.

The BBC Plus Micro contains two VIAs. One (IC20) is dedicated to internal system operation, the other (IC10) is available for system expansion.

Port A of the system expansion VIA is used to provide a centronics standard parallel printer interface, with the octal buffer IC5 being used to buffer the data lines. Port B is left uncommitted and is free for use by the user for input or output purposes.


74LS374 (TTL Octal tri-state D-type flipflop)
Latches A0-A7 when a slow peripheral (VIAs, ADC, 1MHz bus) is accessed.


74LS245 (TTL Octal transceiver)
Buffers the 1MHz extension bus data lines.


74LS244 (TTL Octal buffer)
Buffers the Tube address lines.


74LS245 (TTL Octal transceiver)
Buffers the Tube data lines.


8271 (Floppy Disc Controller, FDC) (8271 Disc Interface Only)
IC15 is a floppy disc drive controller circuit which used to interface to one or two single or double sided 5.25 or 8 inch floppy disc drives. Logic signals from the controller to the disc drive are buffered by two Open collector driver packages IC7 and IC8. The incoming signal from the disc drive is first conditioned by monostable IC1 producing a pulse train with each pulse of fixed width. These pulses are then fed to the data separation circuits ICs 2 and 9. This is a digital monostable. IC4 divides the 8MHz clock signal down to 31.25kHz. IC3 is used to detect index pulses coming in from the drive which show that the drive is ready for a read or write operation.


1770 (Floppy Disc Controller, FDC)
Can be fitted as an alternative for the 8271 FDC. The 1770 allows recording and reading double-density (MFM) discs.


74LS174 (TTL Quad D-flipflop) (1770 Disc Interface Only)


74LS163 (TTL Synchronous binary counter with preset)


74LS00 (TTL Quad 2-input NAND gate)


6522 (Versatile Interface Adapter, VIA)
This is the Versatile Interface Adapter used for internal system functions. Port A of the system VIA acts as a slow data bus which connects to the keyboard, the sound generator (IC38) and speech system chips (IC29, IC37). Port B drives an addressable latch (IC30) which is used to provide read and write strobe signals for the speech interface, the keyboard and the sound generator chip. Also, coming from this latch are control lines C0 and C1 which indicate the amount of RAM devoted to the display memory to be 16K, 8K, 10K or 20K. Pins 6 and 7 of the addressable latch drive the caps lock and shift lock LEDs on the keyboard. Two I/O lines on Port B are used to input the two 'fire button' signals from the paddle connector SK6 and two more lines are used as response lines from the speech interface. Each time the system VIA is written to, the latch connected to port B is strobed by a flipflop (half of IC31) which is triggered from the 1MHz clock signal.


74LS138 (TTL 3-to-8 decoder/latch)
Used in address decoding for the I/O devices.


74LS30 (TTL 8-input NAND gate)
Used in address decoding for the I/O devices.


74LS32 (TTL Quad 2-input OR gate)


74LS04 (TTL Hex inverter)


74LS109 (TTL Dual J-K flipflop)
Performs switching the system clock to 1MHz when a slow peripheral is accessed.


74S04 (TTL Hex inverter)


74LS00 (TTL Quad 2-input NAND gate)


74LS139 (TTL Dual 2-to-4 line decoder)
Used in address decoding for the JIM, FRED and SHEILA pages (&FC, &FD and &FE).


TMS 5220 Speech processor
The speech system device used is a TMS 5220 (IC29) which, on instructions from the Micro, will produce at its output 'canned' speech from its associated memory (IC37) or from speech data fed to it directly from the Micro. The audio output of the speech system is filtered such that it has a cutoff frequency of 7kHz.


74LS259 (TTL 8-bit adressable latch)
See IC20.


74S74 (TTL Dual D-flipflop)
Part of the system clock circuit.


74LS374 (TTL Octal D-flipflop)
Latches the chip select signals for a number of slow peripherals.


74S02 (TTL Quad 2-input NOR gate)
Part of the system clock circuit.


74LS08 (TTL Quad 2-input AND gate)


DNFS 3.0 ROM (8271 Disc Interface Only)
Also fitted for Econet.


16R4 (Programmable Array Logic, PAL)
This is a device that combines a large number of logic gates. In the BBC Plus it is used to drive the ROM and RAM bank switching (see IC71 and DRAM), and do some address decoding.


TMS6100 Speech memory
See IC29


IC38 is a four channel sound generator chip which may be programmed to generate sounds of varying frequency and amplitude on each channel. A quad opamp (IC47) performs mixing the sound generator and speech generator (IC29, IC37) signals, amplifies and filters the result, and feeds it to IC77. Link S17 can be used to switch the Analog line on the 1MHz extension bus from an input being mixed with the other sounds, to output.


74LS139 (TTL Dual 2-to-4 line decoder)
Decodes addresses within page &FE for some peripherals.


74LS20 (TTL Dual 4-input NAND gate)


74LS30 (TTL 8-input NAND gate)


6512A (Central Processing Unit, CPU)
The microprocessor used in the BBC Plus is a 6512A running at 2MHz. It gets slowed down to 1MHz when addressing slow devices such as the 1MHz Extension Bus, the Analogue to Digital Convertor (ADC), and the Versatile Interface Adapters (VIA). A 16MHz crystal oscillator is used to provide clock signals for the CPU in conjunction with divider circuitry in the video processor ULA (IC53) which produces 8, 4, 2 and 1 MHz signals.
Requests for a 1MHz processor cycle from the address decoding (IC41) are fed via to a D-flipflop (half of IC25) which latches the request for a 1MHz cycle. At the appropriate time, as governed by the 2MHz clock, one of the 2MHz clock cycles is masked off by a set/reset-flipflop (half of IC33). When this happens the D-flipflop that latched the request is cleared, to reenable the 2MHz CPU clock at the next appropriate clock phase.


A 555 timer circuit (IC43) provides a reset signal at power up or when the reset key is pressed. Also on the circuit board is a power up reset CR circuit from the +5 volt power supply (C3, R17 and D2). This provides a signal called Reset A which is fed to the system VIA (IC20). Whilst the 555 timer produces a general reset both at power up and when the reset key is pressed, the CR signal Reset A only goes low at power up. By interrogating IC20 on the occurrence of a general reset, the system can thus detect whether this is a cold start, i.e. power up, or a hot start, i.e. the BREAK key or reset switch being pressed when the system has already been in use.


See IC71


74LS163 (TTL Synchronous binary counter with preset)
Used in conjunction with IC46 to switch one of ICs 35, 44, 57, 62, 68 and 71 into the address range &8000-&BFFF. See IC71


74LS138 (TTL 3-to-8 line decoder)
See IC45


LM324 (Quad OPAMP)
See IC38


74LS10 (TTL Triple 3-input NAND gate)


74LS245 (TTL Octal transceiver)
Buffers and enables the RAM data lines to the system data bus. Is disabled when the CRTC accesses the RAM.

IC50, IC51, IC72, IC73, IC74, IC75

74LS253 (TTL Dual 4-channel multiplexer)
These are used to switch the DRAM address lines between the 6512 CPU (IC42) and the 6845 CRTC (IC78), and at the same time perform the Row and Column Address multiplexing.


74S00 (TTL Quad 2-input NAND gate)


5C094 (Video ULA)
The video processor device (IC53) is a custom Uncommited Logic Array (ULA) developed especially for use in the BBC Micro (models A, B and B+). At the end of each CRTC 250nS access period, it latches the byte from the RAM and, according to the display mode in operation, serialises the byte into 1 bit stream of 8 bits or 2 bit streams of 4 bits etc. In this-way, display modes varying in width from 640 pixels in 2 colours to 160 pixels in 8 colours, which may or may not be flashing, can be produced. Also, in the video processor is a high speed piece of static RAM called a palette. This memory can be programmed to define the relationship between the logical colour produced by the RAM and the physical colour which will appear on the display. Thus, in a 640 pixel mode, the two colours to appear on the display need not be black and white, they may be, say, red and blue. Note that the data in RAM is unchanged by the palette, it is the mapping onto physical colours which changes.
Modes 0 through 6 in the Micro are so-called bitmapped screens, which allow for raster graphics. With these screens, each pixel on the screen corresponds directly with one, two or four bits in the video memory. This method of producing video screens is expensive in memory, involving a minimum of 8 kilobytes for the display, though in the BBC Plus this can be allocated in Shadow Screen RAM instead of having the screen and program memory split up the 32k RAM available in the Model B.


74LS273 (TTL Octal latch)
See IC59

IC55, IC56, IC60, IC61, IC64, IC65, IC66, IC67 not fitted in this image

4164-12 (64k x1 DRAM)
Random Access Memory on the Micro is provided by 8 dynamic memory devices (DRAM).

In order to reduce the external pin count and simplify the internal architecture of DRAM devices, their address inputs are usually multiplexed. The 64kbit devices used in the BBC Plus require 16 address lines, but by virtue of this multiplexing only 8 pins are required. Addressing is achieved by first offering the lower 8 bits of the address which are then latched by the DRAM on a Row Address Strobe (RAS) signal, after which the high 8 bits of the address are set up and latched by a Column Address Strobe (CAS) signal. At this point the required address is complete, and data can be read or written. This sounds like a time-consuming process, but by running the address multiplexing at twice the speed of the system clock the DRAM data stays in step with the rest of the system.

In the Micro, the RAS and CAS signals are generated from the 8, 4 and 2 MHz clock signals by IC31, and parts of ICs 23, 33 and 52.
Two devices may have control of the RAM address lines: the 6512 CPU (IC42) and the 6845 CRTC (IC78). The CRTC generates the raster scan signals for the video display, together with the address for each memory mapped byte of information in the RAMs which is required to refresh the display.

The 64kB RAM fitted in the BBC Plus is split into two banks. One is mapped to the range &0000-&AFFF, the other to &3000-&7FFF. The second bank can only be used as screen memory, and only when "shadow mode" is enabled. As shadow screen memory it is not directly accessible from a program running in "normal" memory, instead requiring bank switching. Programs that manipulate video by reading or writing screen memory directly will not work with shadow mode video screens; all video memory reads and writes have to go through the OS. The advantage of shadow screen memory comes from having 32kB RAM available to user programs, independently of the video mode selected. Shadow memory switching is done largely by the PAL IC36.


1770 DFS ROM (1770 Disc Interface Only). Note in this picture that the DFS ROM is not fitted.




SAA5050 (Teletext Character Generator)
Display mode 7 is a Teletext character mode. When using this mode, only 1K of RAM is devoted to the display memory and the characters are held within it as ASCII bytes. To implement this an SAA5050 Teletext character generator is used. IC54 latches the DRAM data going into the SAA5050, which then translates these bytes into a standard Teletext/Prestel format display.
A 6MHz clock signal is required for the operation of this device. This signal is produced using two inverters, two R/C delays, a set-reset flipflop (half of IC52), then EXORing this signal with the 2MHz clock.


Socket DIL 28P ROM socket.


74LS86 (TTL Quad 2-input EXOR gate)


Socket DIL 28P ROM socket.


74LS74 (TTL Dual D-flipflop)


74LS123 (TTL Dual monostable multivibrator, MMV)


23256 OS/BASIC ROM (B+)
Apart from the OS/BASIC ROM, five other ROMs (ICs 35, 44, 57, 62 and 68) can be on the main circuit board.
Overall address decoding for the ROMs is by ICs 22, 28, 34 and 40 which decode memory addresses &8000-&BFFF and &C000-&FFFF. The operating system occupies the address range &C000-&FFFF; the address range &8000-&BFFF can be occupied by one of the installed additional ROMs by means of 'bank switching', which is effected by ICs 45 and 46. This allows for different programming languages, system software extensions such as a Disc Filing System, or application software like a word processor to be installed, and be activated when needed. The OS and BASIC are contained in one physical ROM, but the bank switching treats the range &8000-&BFFF as logically identical to any of the additional ROMs.
Each of the auxiliary sockets can contain 8kB, 16kB or 32kB devices, where the latter are treated as two 16kB devices. This is done by connecting IC45 QA to A14 of any 32kB ROMs fitted.
Link S13 can be used to assign bank number 0/1 or 14/15 to the BASIC ROM. This allows other ROMs to have precedence on startup.


74LS283 (TTL 4-bit binary adder)
Used in conjunction with IC36 and the signals C0 and C1 out of IC30 to map the CRTC address lines to the correct DRAM starting address.


IC77 provides audio power amplification to drive a speaker (connected to PL15).


6845 (CRT controller, CRTC) This is the heart of the BBC Micro's video circuitry. Its major function is that of displaying the video data in memory on a raster scan display device such as a television or monitor. As a bonus, the sequential nature of accessing the system RAM for the video display refreshes all the DRAM storage.
The CRTC does not interfere with CPU access to the memory, as they operate on alternate phases of the system clock.
The 6845 is responsible for producing the correct format on the display device, positioning the cursor, and monitoring the light pen input. Other video functions involving colour and Teletext are dealt with by the video ULA (IC53) and the Teletext Character Generator (IC59).


74S74 (TTL Dual D-flipflop)


74LS244 (TTL Octal buffer)
See IC81


68B54 (Advanced Data Link Controller Circuit, ADLC)
ICs 70, 80, 81, 88, 91, 92 and 93 are concerned with the Econet interface.
IC81 is an Advanced Data Link Controller Circuit, type 68B54 which handles the synchronous high-speed serial data transmission that is the basis of the Econet protocol. Data to be transmitted on to the network is fed from the ADLC to the line driver circuit, IC91, which is enabled from the RTS line on IC81 via a MMV (half of IC88). Transmit data then goes through the line driver circuit which produces a differential signal drive to the Econet cables. Received data is detected and converted to a logic signal by one half of IC92, a LM319 dual comparator. The received data is then fed back to the data link controller circuit.
An Econet installation has a single master clock station which provides the clock for the whole of the network. This clock signal is transmitted around the network as a second differential line signal and is used to clock the data in and out of the data link controller circuits. The network clock is also detected using one half of a LM319 comparator circuit, and the detected clock is then fed to both receive clock and transmit clock inputs on the 68B54. In the presence of a network clock, a MMV (the other half of IC88) is permanently triggered providing a data carrier detect signal for the ADLC. Once the network clock is removed, the monostable immediately drops out and the data carrier is no longer detected.
Econet is a broadcast network system on which a number of stations may attempt to transmit their data over the network at any given time. In this setup, a situation called a collision can occur when two or more stations transmit at the same time. The transmitting stations should detect the collision and back off before attempting to repeat the transmission. Collision arbitration software is included in the Econet system. Collisions on the network data lines result in the differential signal on the two data wires being reduced. This condition is detected by IC93 which is another dual comparator circuit. When there is a good differential data signal on the network, one of the outputs of IC93 will be low, in which case the output of IC91 pin 6 will be high, indicating no collision. When there are no collisions on the network, and the network clock is detected by the clock monostable, the data link controller is clear to send data over the network. When there is a collision on the network both outputs of IC93 will go high and the clear to send condition will cease. Note that on the BBC Plus, the collision detect circuitry is not normally fitted; instead the software protocols take care to prevent collisions by detecting a "line free" situation before starting transmission.

On receiving data, the data link controller circuit produces interrupts which are tied to the central processor NMI line. These interrupts are disabled by one half of the dual D-flipflop IC69. Once in the data link controller interrupt service routine, IC69 is reset, enabling further interrupts.

Each Econet system requires termination at the two extreme ends of the network. With the BBC+ this, as well as the Econet clock, has to be provided externally.

Up to 253 (the numbers 0 and 255 being reserved, and the use of number 1 discouraged) stations may be connected to each Econet section with each station being identified by a unique station identification number. This station ID is programmed on the links into IC96, which can be read by enabling the octal buffer.


6850 (Asynchronous Communication Interface Adapter, ACIA)
This device is used to buffer and serialise or deserialise the audio and RS423 data. It is used in conjunction with another ULA (IC85) specifically designed for the BBC Micro (models A, B and B+). Contained within this ULA is a programmable baud rate generator, a cassette data/clock separator and switching to select either RS423 or cassette operations. IC18 divides the main board 16MHz clock by 13 which is then divided further within the serial interface ULA to produce the 2400/1200 Hz cassette signal. Automatic motor control of an audio cassette recorder is achieved by a small relay driven by a transistor from the serial interface ULA. The signal out of the cassette is buffered and the incoming signal is suitably filtered and shaped by a three stage amplifier, implemented using a LM324 quad opamp (IC89).

IC83, IC86

74LS86 (TTL Quad 2-input EXOR gate)
Used for colour generation on composite video. See IC53


uPD7002 (Analogue to Digital Converter, ADC)
A four channel ADC facility with 10-bit resolution is provided by IC84. This device connects straight to the Micro's data bus and is a dual slope convertor with its voltage reference being provided by the three diodes, D9, D10 and D11.


2C199 (Serial ULA)
See IC82

IC87, IC90

74LS00 (TTL Quad 2-input NAND gate) Used for colour generation on composite video. See IC53


74LS123 (TTL Dual monostable multivibrator, MMV)


LM324 (Quad OPAMP)
See IC82


SN75159N (Differential line driver)
See IC81

IC92, IC93

LM319 (Dual comparator)
See IC81


88LS120 (RS423 receiver)
The RS423 Transmit and Receive data signals and the Request-To-Send and Clear-To-Send flow control signals are interfaced by ICs 94 and 95 which translate between TTL and standard RS423/232 signal levels. Note that this is one of the few sections of circuitry on the Micro which requires an additional -5v supply to be present.


DS3691 (RS423 driver)
See IC94


TM4164EK8-12 (Optional)
Alternate fitment for the 8 DRAM chips IC54, IC55, IC60, IC61, IC64, IC65, IC66 and IC67.


Disc Drive connector
34way IDC header
0V 1 2notSSEL 8"
0V 3 4(notINX 8")
0V 5 6NC
0V 7 8notINX 5 1/4"
0V 910notS0
0V2728notWR PCT
0V3132notS/SEL 5 1/4"
0V3334(notRDY 8")


Printer connector
26way IDC header
STB 1 20V
PA0 3 40V
PA1 5 60V
PA2 7 80V
PA3 9100V


User Port connector
20way IDC header


1MHz Bus connector
34way IDC header
0V1516audio in/out (S17)
The address and data lines, A0-A7 and D0-D7, together with some page select and control lines are available as the 1MHz extension bus to which various peripheral devices may be connected, e.g. a Teletext interface. All accesses to this bus will be at 1MHz processor speed. The octal buffer IC71 and the octal transceiver IC72 are used to interface these signals to the internal data and address buses. There is also a provision for an audio signal, which can be either output from the peripheral to the B+'s internal amplifier, or output from the B+ to the expansion, selectable via S17.


Tube Connector
40way IDC header
Selected address and data lines are available on the Tube connector which is used to connect auxiliary processors into the system. This should only be used by Acorn designed peripherals.


Keyboard connector


Speaker connector (PL15)

Power Supply

0v and +5v

Power Supply

+5v and 0v

Power Supply

+5v and 0v

Power Supply



Miniature relay, normally open, used to control the cassette recorder motor.


Shunts S19 18 15 12 11 9


UHF TV modulator


Composite Video Out BNC connector.


RGB output connector
MAB6H 6 pin DIN
The red, green and blue logic signals produced by the video processor are buffered by transistors Q1, 2 and 3 and fed out together with a composite sync signal to the RGB connector (SK3). This output is suitable for feeding straight to the gun drives of RGB monitors. The red, green and blue lines are summed together by binary weighted resistors to feed Q7 which produces a 1V composite video signal suitable for feeding to a monochrome monitor, on which the different colours will appear as different intensities. By closing S26 the chroma signal present at Q9 will be added to this signal, enabling colour display on suitable monitors.
The red, green and blue signals are summed with slightly different weight factors to provide the input signal for the UHF modulator. The chroma signal is always present here. The output of the UHF modulator is a TV signal on channel 36, suitable for feeding to the aerial input of a domestic television.


RS423 connector
MAB5WH 5 pin DIN
RS 423


Cassette connector
MAB7SH-L 7 pin DIN


Analogue connector
15-pin female D type
Analogue in
+5V19light pen strobe in
GND210fire button 1
analogue in CH3412analogue in CH2
analogue GND513fire button 0
analogue in CH1715analogue in CH0
analogue GND8


Econet 5-way Din Plug
[Back to Insides]
Back to 8BS